Configurable Decoder for Pin-Limited Applications

LSU Reference: 0624



  • Under patent prosecution


Pin limitation is a major performance and size bottleneck in IC chips, including in FPGAs. This invention is a configurable decoder which, for pin-limited environments, efficiently translates a limited number of input signals into a large number of output signals. In contrast to current approaches, this technology allows flexibility and re-configurablility, without incurring high costs in terms of performance impact, gate count and manufacturing expense. It also provides techniques for reducing gate count requirements of 1-hot decoder implementations.


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